The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS circuit. Certain improvements in performance of FET ICs can be realized by forming the FETs in a thin layer of semiconductor material overlying an insulator layer. Such semiconductor on insulator (SOI) FETs, among other benefis, exhibit lower junction capacitance and hence can operate at higher speeds.
The MOS transistors formed in and on the SOI layer are interconnected to implement the desired circuit function. A number of voltage busses are also connected to appropriate devices to power those devices as required by the circuit function. The voltage busses may include, for example, a Vdd bus, a Vcc bus, a Vss bus, and the like, and may include busses coupled to external power sources as well as busses coupled to internally generated or internally altered power sources. As used herein, the terms will apply to external as well as internal busses. As various nodes in the circuit are either charged or discharged during the operation of the circuit, the various busses must source or sink current to those nodes. Especially as the switching speed of the integrated circuits increases, the requirement of sourcing or sinking current by a bus can cause significant voltage spikes on the bus because of the inherent inductance of the bus. To avoid logic errors that might be caused by the voltage spikes, it has become commonplace to place decoupling capacitors between the busses. For example, such decoupling capacitors can be connected between the Vdd and Vss busses. These decoupling capacitors are typically distributed along the length of the busses. The capacitors are usually formed as MOS capacitors with one plate of the capacitor formed by the same material used to form the gate electrode of the MOS transistors, the other plate of the capacitor formed by an impurity doped region in the SOI layer, and the dielectric separating the two plates of the capacitor formed by the gate dielectric.
One problem with such decoupling capacitors formed in the conventional manner is the size of the capacitors. There is a continuing effort to reduce the size of integrated circuit components so that an ever increasing number of components can be fabricated on a semiconductor chip of a given size. The size of the conventionally fabricated decoupling capacitors is an impediment to the continuing effort. To increase the capacitance per unit area of a conventionally fabricated decoupling capacitor, which would allow a reduction in capacitor size, the thickness of the capacitor dielectric must be reduced. Reducing the thickness of the capacitor dielectric leads to problems of increased capacitor leakage current as well as reduced reliability. Additionally, it is disadvantageous to require that the same dielectric material be used for both the gate dielectric of MOS transistors and for the capacitor dielectric because such requirement limits the flexibility of the fabrication process.
Accordingly, it is desirable to provide a method for fabricating an integrated circuit that includes high capacitance per unit area capacitors without resorting to very thin dielectric layers. In addition, it is desirable provide methods for fabricating integrated circuits including capacitors in which the capacitor dielectric is formed separately from the gate insulator of MOS transistors of the IC. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.